← AlpineLogicFSM Studio

Visual FSM editor · FPGA / ASIC workflows

Design FSMs like your silicon thinks.

Draw states and transitions, write Verilog-style conditions and outputs, then step cycles in simulation and peek at generated Verilog—all in one focused workspace.

Download for desktopSee how it works
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Image: Hero: main editor + simulation.

Who it's for

  • Hardware and FPGA engineers sketching control FSMs before RTL.
  • Students and educators teaching Moore vs Mealy and guarded transitions.
  • Anyone who wants graph-first FSM tooling with cycle-accurate stepping and code preview—not a generic flowchart toy.

Why FSM Studio

Graph-first, not slide-first

Add states, wire transitions, and reshape connections with bend handles. The diagram stays the center of gravity—no fighting a generic diagram tool.

Moore or Mealy, on purpose

Switch modes and edit state outputs (Moore) or transition outputs (Mealy) in a dedicated inspector. The tool stays honest about what each paradigm means.

From diagram to Verilog-shaped thinking

Guards and outputs use expressions that fit a hardware mental model—including multi-output assignments when you need them. Static checks catch issues before you export or simulate.

Step the clock. Watch the FSM.

Turn on Simulation mode, drive inputs per cycle, and advance with Step (or keyboard shortcuts). The canvas highlights current state, next-state preview, and firing transitions so behavior isn't abstract—it's visible.

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Image: Simulation + firing transition.
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Image: I/O signals + widths.

Name your I/O like the block on the whiteboard.

Define inputs and outputs with names and bit widths (1–256). Reorder ports with a simple drag interaction. Your diagram, conditions, and Verilog preview stay aligned to the same signal list.

Catch structural mistakes early.

Built-in static analysis helps you find incomplete or inconsistent FSM structure before you rely on it in a larger design. Less thrashing between tools; more confidence in the graph you're about to hand off or implement.

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Image: Static check results.
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Image: Verilog preview.

Peek at generated Verilog.

Open a Verilog preview generated from your project so you can sanity-check naming, case structure, and how Moore outputs map into always_comb style logic. Scope and completeness of codegen may evolve; think of it as a preview and starting point, not a full synthesis replacement.

Save and reopen your work.

Projects persist as structured files (JSON). On desktop, use the native file dialog to open and save—your FSMs belong in your repo or project folder, not only in a browser tab.

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Image: Project files.

Diagram helpers for real-world graphs.

Model merge hubs and global-condition constructs when your control story isn't only one guard per edge. The editor explains how those edges behave in checks, simulation, and codegen—so the diagram stays expressive without hiding semantics.

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Image: Merge / global guard.

Built for responsiveness at scale

FSM Studio is built as a fast desktop-class app (React + TypeScript UI, Tauri + Rust engine path) so interaction, simulation, and checks stay responsive as graphs grow.

Built with
ReactTypeScriptTauriRust
Logo strip: use official marks only where guidelines allow; text-only placeholders for now.

Distribution (Mac / Windows / Linux), installers, and pricing are not finalized—this CTA is a placeholder for when builds ship.

FAQ

Is this a general-purpose flowchart tool?
No. It’s specialized for finite state machines with guarded transitions and hardware-oriented outputs.
Moore vs Mealy—do I have to choose?
Yes. Pick a mode so outputs are edited and interpreted consistently—like you would in RTL documentation.
Can I use it in the browser?
The product can be explored in a web dev workflow; the recommended experience for full file integration is the desktop build.
Does it replace my EDA toolchain?
It’s a design and communication tool plus preview—a bridge from whiteboard to Verilog-shaped thinking, not a full synthesis or place-and-route replacement.

FSM Studio — visual finite-state machine editor and simulator for people who think in states, guards, and hardware-style outputs.

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